Design & Reuse
Catalog of SIP Cores
System on Chip design resources
arrow CEI (10)
arrow Cell / Packet (6)
arrow Error Correction/Detection (152)
arrow Ethernet (177)
arrow Fibre Channel (1)
arrow HDLC (6)
arrow Interleaver/Deinterleaver (1)
arrow Modulation/Demodulation (22)
arrow Optical/Telecom (35)
arrow Other (15)
152 IP
51
6.0
LTE turbo decoder
TC7000-LTE is a convolutional turbo code (CTC) decoder optimized for FPGAs. Its unique pipe-line architecture enables to reach very high clock frequen...
52
6.0
LTE/NR Small Block Lengths Decoder
TC5390 is a decoder IP Core compliant with the small block lengths coding scheme for UCI as defined by 3GPP 4G-LTE and 5G-NR specifications. A single...
53
6.0
ITU-Ghn LDPC Encoder / Decoder
TC4400 is a LDPC decoder core that is fully compliant with ITU G.hn (wireline home networking) specifications. It support a decoded throughput up to 1...
54
6.0
DVB-RCS2 turbo decoder
TC1620 is a high performance turbo decdoer Core compliant with DVB-RCS2 specifications. Ideally suited fo systems requiring flexibility, short/medium ...
55
6.0
DVB-S2X decoder
TC4000 is fully compliant with DVB-S2 and DVB-S2X specifications, covering modulations up to 256APSK. It performs I/Q demapping, Block deinterleaver,...
56
5.0
100 Gbit/s IEEE 802.3bj RS Encoder and Decoder
IEEE 802.3bj was developed in response to the rapid growth of server, network and internet traffic. The standard meets the need for higher data rates ...
57
5.0
BCH Decoder
A highly configurable hardware IP core that performs error detection and correction using Bose–Chaudhuri–Hocquenghem (BCH) codes. It detects and corre...
58
5.0
BCH Encoder
A fully parameterizable SystemVerilog IP core implementing systematic encoding for binary BCH (Bose-Chaudhuri-Hocquenghem) codes. The core supports ar...
59
5.0
CCSDS 131.2 Wideband Demodulator
The Creonic CCSDS high performance wideband demodulator performs all tasks of an inner receiver. It allows for processing symbol rates of 500 Msymb/s ...
60
5.0
CCSDS 231.0 LDPC Encoder and Decoder
The CCSDS 231.0 LDPC IP supports the LDPC coding schemes as defined by the CCSDS standard. The LDPC codes with rate 1/2, coded block lengths 128 and 5...
61
5.0
CCSDS AR4JA LDPC Decoder & Encoder IP Core
AR4JA LDPC decoder is a configurable design that allows runtime configuration for decoding different code rates (i.e., 1/2, 2/3 and 3/4). To obtain hi...
62
5.0
CCSDS AR4JA LDPC Encoder & Decoder
The Creonic CCSDS AR4JA LDPC IP supports the LDPC coding schemes as defined by the CCSDS standard. The LDPC codes with rates 1/2, 2/3 and 4/5, block l...
63
5.0
CCSDS SCCC Turbo Encoder and Decoder
The recommended CCSDS 131.2-B-1 standard introduces a Serial Concatenated Convolutional Code (SCCC). Main goal of this code is to allow an efficient u...
64
5.0
4G LTE/LTE-A Turbo Decoder
LTE and LTE Advanced (LTE-A) are the mobile broadband standards of the 4th generation. Current LTE installtion provides data rates of up to 300 Mbit/s...
65
5.0
DVB-RCS2 Turbo Decoder
DVB-RCS2 (Digital Video Broadcast - Second Generation DVB Interactive Satellite System) is the latest ETSI standard of the second generation for digit...
66
5.0
DVB-S2X Wideband LDPC BCH Decoder IP Core
The DVB-S2X Wideband LDPC Decoder is a powerful FEC core decoder for Digital Video Broadcasting via Satellite. It implements extensions to the DVB-S2 ...
67
5.0
DVB-T2 Demodulator and LDPC/ BCH Decoder IP Core
The demodulator is designed to be used together with an RF tuner, and an analog to digital converter. The system has an internal state machine to cont...
68
4.0
LDPC Decoder for DVB-T2/T2-Lite
In Digital video broadcasting for terrestrial broadcasting systems, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Density Parity Chec...
69
4.0
LDPC Decoder for IS-GPS-800D Applications
The IS-GPS-800D standard defines an irregular Parity Check Matrix (PCM) for 2 subframes (2 and 3) encoded using Low Density Parity Check (LDPC) Forwar...
70
4.0
Highly Integrated Reed Solomon Codec
ntRSC_IESS core is a highly integrated solution implementing a time-domain Reed-Solomon Forward Error Correction algorithm. The core supports several ...
71
4.0
Non-binary LDPC Decoder
A powerful Forward Error Correction (FEC) subsystem is needed in almost all wireless communication systems. Low-Density Parity-Check (LDPC) codes are ...
72
4.0
Configurable Reed Solomon Decoder
Highly configurable Reed Solomon Decoder compliant with the requirements of nearly all modern standards using Reed-Solomon error correction....
73
4.0
Configurable Reed Solomon Encoder
A fully configurable Reed Solomon Encoder compliant with the requirements of nearly all modern standards that use Reed-Solomon error correction....
74
4.0
Configurable Turbo Product Codec
In channel coding redundancy is inserted in the transmitted information bit-stream. This redundant information is used in the decoder to eliminate the...
75
4.0
Configurable Viterbi Decoder
Highly configurable Viterbi Decoder compliant with the requirements of nearly all modern standards using Viterbi error correction....
76
4.0
Fully Configurable LDPC Encoder
In channel coding redundancy is inserted in the transmitted information bit-stream. This redundant information is used in the decoder to eliminate the...
77
3.0
100G Reed-Solomon Codec for Ethernet IEEE 802.3 Clause 91 (803.3bj)
The RS100-160 core implements the codec for the Forward Error Correction (FEC) cyclic code RS(528, 514, 7,10) used in the IEEE 802.3bj (100G Backplane...
78
3.0
66/2112 Codec for Cyclic Code (2112,2080)
The CEC1-66/2112 core implements the codec for the Forward Error Correction (FEC) cyclic code (2112,2080) used in the IEEE 802.3ap (10G Backplane Ethe...
79
3.0
BCH Encoder/Decoder
The binary BCH decoder has four main functional blocks along with memory blocks: 1. Syndrome calculation block: identifies the presence of errors in ...
80
3.0
NCR Processor
NCR (Network Clock Reference) is a procedure to provide the master clock (i.e. time information) of the satellite to all its user terminals. Typically...
81
3.0
High-Performance Lossless Compression Core
Lossless data compression is a class of data compression algorithms that allows the exact original data to be reconstructed from the compressed data. ...
82
3.0
Open Source Viterbi Decoder (AXI4-Stream compliant)
Convolutional codes are widely adopted in wireless communication systems for forward error correction. Creonic offers you an open source Viterbi decod...
83
3.0
DVB-S2 BCH and LDPC Encoder and Decoder
DVB-S2 (Digital Video Broadcast - Satellite 2nd Generation) is an ETSI standard of the second generation for digital data transmission via satellites....
84
2.0
2.3 Gbit/s DOCSIS 3.1 Downstream LDPC Decoder (PLC, NCP, Data)
Data Over Cable Service Interface Specification (DOCSIS) is an international telecommunications standard that permits the addition of high-bandwidth d...
85
2.0
CCSDS LDPC
...
86
2.0
LDPC Decoder for DVB-C2
In Digital video broadcasting for cable systems systems, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Density Parity Check) codes c...
87
2.0
Reed Solomon Encoder/Decoder
- The Reed Solomon Encoder is fed with an input message of K information symbols, the Encoder appends 2T parity symbols to the input message in order ...
88
2.0
IEEE 802.11ad (WiGig) LDPC Decoder
The WiGig standard (IEEE 802.11ad) delivers data rates of up to 7 Gbit/s and hence outperforms the current IEEE 802.11n standard by more than 10x. It ...
89
2.0
IEEE 802.15.3c (60 GHz PHY) Multi-Gbit/s LDPC Decoder
The IEEE 802.15 working group specifies standards targeting the wireless personal area network (WPAN). Task group 3 of the working group focuses on hi...
90
2.0
Viterbi Decoder
Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors...
91
2.0
Fixed-Point AWGN Channel
The Creonic AWGN Channel IP is a noise generator capable of processing up to a maximum of 512 symbols in parallel. The IP was developed with the aim o...
92
2.0
GMR Release 2 and GMR Release 3 LDPC Decoder
GEO-Mobile Radio (GMR) is an ETSI standard for satellite phones. The Creonic GMR Decoder IP core supports the PNB2 burst packets that were added in GM...
93
2.0
LTE Turbo decoder
This block is suitable for 3GPP Long Term Evolution (LTE) applications compatible with the 3GPP Technical Specification. The LTE Release-8 Turbo code ...
94
2.0
DVB-C2 Receiver (including LDPC and BCH decoder)
DVB-C2 (Digital Video Broadcast - Cable 2nd Generation) is an ETSI standard of the second generation for digital data transmission via cable networks....
95
2.0
DVB-RCS Turbo Decoder
DVB-RCS (Digital Video Broadcasting - Interaction channel for satellite distribution systems) is an established ETSI standard for digital data transmi...
96
1.0
Medium throughput, compact Reed Solomon decoder
This implementation of a M=8 Reed Solomon decoder has been designed to use a minimum set of resources whilst maintaining a medium throughput and flexi...
97
1.0
High Throughput Reed Solomon Decoder
This is a Reed Solomon decoder capable of operating with shortened codewords. The basic mother rate is (N,K) = (255,239) which has 16 parity bytes an...
98
1.0
High-throughput Low-memory Viterbi Decoder
This IP core is available in either normal or high throughput configurations. The normal configuration instances a single fully parallel stage, equiva...
99
1.0
Ultra Low-power, compact Hybrid Viterbi Decoder
This IP core is available with a configurable number of ACS units to suit a range of throughput requirements. The default configuration instances 4 AC...
100
1.0
HomePlug Turbo Decoder
On the transmitter side, the PHY layer receives its inputs from the Media Access Control (MAC) layer. There are three separate processing chains: A) H...